In the manufacture of integrated circuits, copper interconnects are generally formed on a semiconductor substrate using a copper dual damascene process. Such a process begins with a trench being etched into a dielectric layer and filled with a barrier layer, an adhesion layer, and a seed layer. A physical vapor deposition (PVD) process, such as a sputtering process, may be used to deposit a tantalum nitride (TaN) barrier layer and a tantalum (Ta) or ruthenium (Ru) adhesion layer (i.e., a TaN/Ta or TaN/Ru stack) into the trench. The TaN barrier layer prevents copper from diffusing into the underlying dielectric layer. The Ta or Ru adhesion layer is required because the subsequently deposited metals do not readily nucleate on the TaN barrier layer. This may be followed by a PVD sputter process to deposit a copper seed layer into the trench. An electroplating process is then used to fill the trench with copper metal to form the interconnect.
As device dimensions scale down, the aspect ratio of the trench becomes more aggressive as the trench becomes narrower. This gives rise to issues such as trench overhang during the copper seed deposition, leading to pinched-off trench openings during plating and inadequate gapfill. Additionally, as trenches decrease in size, the ratio of barrier metal to copper metal in the overall interconnect structure increases, thereby increasing the electrical line resistance and RC delay of the interconnect.
One approach to addressing these issues is to reduce the thickness of the TaN/Ta or TaN/Ru stack, which widens the available gap for subsequent metallization and increases the final copper volume fraction. Unfortunately, this is often limited by the non-conformal characteristic of PVD deposition techniques. Accordingly, alternative techniques for reducing the thickness of the barrier and adhesion layer are needed.